We are looking for an ASIC/FPGA Design Verification Engineer.
● Develop verification environments of the block level, subsystems, and full chip.
● End-to-end ownership of the testing process including test plan, Agents implementation, and coverage collection.
● Develop methodologies, scripts, and infrastructure improvements.
● Plan, design, and bring up a complete verification environment from scratch.
● Work closely with RTL & Validation teams.
● BSc/MSc in Computer / Electrical Engineering or equivalent.
● At least 3 years experience in design verification.
● Proficiency with Verilog & System Verilog.
● Proficiency with UVM
● Strong communication skills, both verbal and written (English)
● Rapid learner, Willing to work in a dynamic and demanding environments, Team player who can also work independently
● Professional environment and great colleagues in a stable, multicultural company, with opportunities for long-term professional development
● Standard 40-hour work week; Work-from-home is allowed
● Good work-life balance, including 25 days annual paid leave (increasing with 1 day per year up to 31 in total), flexible working hours
● Additional health and dental insurance
● Food vouchers
● 6 days annual sick leave, without the necessity to present an official sick leave sheet
● Your own training budget (for conferences, courses, etc.)
● Cutting-edge equipment and tools that make you feel more productive
● Financial assistance for car and property credit
● Annual bonus